1. Field of the Invention
The present invention relates to a feed control apparatus for an inductive load forming, for example, an in-vehicle electronic control device, and more particularly, to a feed control apparatus for an inductive load improved so as to suppress a power loss occurring in a feed control circuit part.
2. Description of the Related Art
To a general DC electric load including an inductive load, a reverse-connection protection diode is connected in series in order to prevent a burnout caused by a power-supply short circuit when the power supply is erroneously connected in reverse polarity. Also, a field effect transistor is used to suppress the occurrence of a power loss due to a voltage drop across the reverse-connection protection diode during normal operation when the power supply is connected in proper polarity. For example, according to JP-A-08-308116 (Patent Document 1), as is shown in FIG. 7 of this gazette, a pair of power-supply terminals 2 and 3, to which a DC power supply 1 is connected, is provided, and an FET 10 is connected between a pair of the power-supply terminals 2 and 3 via a circuit 4 as an object to be protected.
By connecting the FET 10 so that there is a directionality in which a current flows from a source to a drain when the DC power supply 1 is connected properly, and by connecting a gate of the FET 10 to one power-supply terminal 2 via a resistor 11, a back-flow prevention circuit having small voltage drop and power loss during normal operation is provided.
In Patent Document 1, an N-channel field effect transistor is employed as a reverse-connection protection element on a downstream side of the DC power supply 1 and the FET 10 is driven to conduct in a direction same as that in an internal parasitic diode.
Also, according to JP-A-2011-200016 (Patent Document 2), as is shown in FIG. 2 of this gazette, back-flow prevention diodes D1 and D2 of FIG. 1 are replaced with MOSFETs, so that in the event of a voltage drop due to an abnormality in one power supply device while power supply devices 1 and 2 are connected in parallel and supplying power to a load device 3, a current is prevented from flowing backward from the other normal power supply device to the power supply device having an abnormality.
In Patent Document 2, for example, P-channel field effect transistors are employed as reverse-connection prevention elements on an upstream side of the power supply devices 1 and 2 and these FETQ1 and FETQ2 are driven to conduct in a direction same as that in internal parasitic diodes.
Meanwhile, according to JP-A-2005-143282 (Patent Document 3), as is shown in FIG. 1 of this gazette, a series circuit made up of a first MOSFET transistor Q1 and a reactance L is connected between a DC power supply B and a load 1. A second MOSFET transistor Q2 is provided between a connection point of the first transistor Q1 and the reactance L and the ground. Both of the transistors Q1 and Q2 are switched ON and OFF by providing a dead period to during which both of the transistors Q1 and Q2 are switched OFF simultaneously using a step-down PWM converter which is installed between a connection point of the reactance L and the load 1 and the ground, and to which a smoothing capacitor C is connected. When configured in this manner, a switching loss is reduced by preventing a current from flowing to parasitic diodes D1 and D2 in the second MOSFET transistor Q2.
In Patent Document 3, the second MOSFET transistor Q2, which is an N-channel field effect transistor, is controlled so as to conduct in a direction opposite to the conduction direction in the parasitic diode D2, so that charges charged to the smoothing capacitor C are discharged quickly.
Reference numerals and signs used in the description of the respective patent documents above are those used in the respective patent documents.
Patent Document 1: JP-A-08-308116 (Abstract, paragraph 0017, FIG. 3, and FIG. 7)
Patent Document 2: JP-A-2011-200016 (Abstract, FIG. 2)
Patent Document 3: JP-A-2005-143282 (Abstract, FIG. 1)
According to Patent Document 1 and Patent Document 2 above, field effect transistors having a small closed-circuit voltage drop are employed instead of back-flow prevention diodes. During normal operation, a gate voltage is continuously applied to the field effect transistor from the DC power supply, so that a current is passed continuously at low power consumption. A field effect transistor can be driven to conduct in either direction between the source terminal and the drain terminal depending on in which manner a gate voltage is provided. When used as an opening and closing element, the field effect transistor is driven in a forward direction so that it is driven to close in a direction opposite to the conduction direction in the internal parasitic diode. On the contrary, when used as a back-flow prevention diode, the field effect transistor is driven in a backward direction so that it is driven in a direction same as the conduction direction in the parasitic diode.
The techniques disclosed in Patent Document 1 and Patent Document 2, however, do not present a concept to employ field effect transistors as a free-wheeling diode for an inductive load.
On the other hand, according to Patent Document 3, the internal parasitic diode in the field effect transistor is used as a free-wheeling diode for an inductive load. A voltage drop by this parasitic diode takes a large value in comparison with a closed-circuit voltage between the source terminal and the drain terminal. Accordingly, there is a problem that power consumption increases when a large current flows and hence a temperature rises high.